In conventional CMOS sensors, the circuitry for several photo-diodes is shared. The pixels may include two photo-diodes located in neighboring rows that share the same circuitry.
Shown in FIG. 1 is a four transistor (4 T) pixel of the conventional CMOS sensor that has global shutter capabilities (i.e. all pixels perform charge integration simultaneously). After charge integration is completed in pinned photodiode 101, the accumulated charge is transferred (via transfer gate transistor 103) into second pinned photodiode 102 where it is stored for readout.
In this conventional system the second pinned photodiode has a higher pinning voltage, or transfer gate 103 has a potential barrier and a well incorporated in it to ensure proper charge transfer. Also, pinned diode 102 is shielded from the impinging photons 115 to prevent undesirable smear effects when the objects in the scene moves. The signal charge readout from second pinned diode 102 then proceeds by first resetting Floating Diffusion (FD) node 104 to the drain bias voltage by momentarily turning on reset transistor 106 followed by pulsing charge transfer transistor gate 105. This sequence then proceeds in a sequential order row by row.
The signal appearing on the FD is buffered by the source follower transistor 107 that is addressed by a row addressing transistor 108. The signals controlling the charge transfer transistor gates, the reset transistor, and the addressing transistor are supplied by the row bus lines 111, 112, 113 and 114 respectively. The Vdd bias is supplied to the pixels by the column Vdd line 109 and the signal output appears on the column output line 110.
Using the pinned diodes for charge storage is advantageous since it is well known that these diodes have a low dark current generation. High dark current in the storage sites would add to noise and would also generate undesirable shading effects in the image.
Unfortunately, the second pinned diode consumes a significant pixel area, thus increasing the size of the sensor and ultimately its cost. Another disadvantage of the pinned PD storage gate approach, is the higher, pinning voltage that is necessary for the storage diode. This utilizes a voltage swing that is determined by the maximum device operating voltage and therefore results in a restriction of charge storage capacity (reduced dynamic range (DR)).